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L9826
Octal Low-Side Driver for Resistive and Inductive Loads with Serial/Parallel Input Control, Output Protection and Diagnostic
Features

OUTPUTS CURRENT CAPABILITY UP TO 450mA TYPICAL RON = 1.5 AT TJ = 25C PARALLEL CONTROL INPUTS FOR OUTPUTS 1 AND 2 SPI CONTROL FOR OUTPUTS 1 TO 8 RESET FUNCTION WITH RESET SIGNAL AT NRES PIN OR UNDERVOLTAGE AT VCC INTRINSIC OUTPUT VOLTAGE CLAMPING AT TYP. 50V OVERCURRENT SHUTDOWN AT OUTPUTS 3 TO 8 SHORT CIRCUIT CURRENT LIMITATION AND SELECTIVE THERMAL SHUTDOWN AT OUTPUTS 1 AND 2 OUTPUT STATUS DATA AVAILABLE ON THE SPI SO20
Description
The L9826 is a Octal Low-Side Driver Circuit, dedicated for automotive applications. Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. Chip Select and Serial Peripheral Interface for outputs control and diagnostic data transfer. Parallel Control inputs for two outputs. .
Order codes
Part number L9826 L9826TR Temp range, C Package SO20 (16+2+2) SO20 Packing Tube Tape & Reel
July 2005
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L9826
Contents
1 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pins Description and Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 4.2 4.3 4.4 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Stages Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power outputs characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 6 7
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package Informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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1 Block Diagram
1
Block Diagram
Figure 1. Block diagram
VCC
VCC
OUT1
1 2 3
NON1
Q1
S
Latch / Driver
R
IOL
Overtemperature Detection
Diag1
Fault Latch
+ -
VDG
CH1 NON2
VCC
Q2 Diag2
CH2
OUT2 OUT3
SPI Interface
Output Latch
NCS
VCC
CLK
VCC
Shift Register
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q3
S
Latch / Driver
IOL
R
+ -
SDI
SDO
VCC
Diag1 Diag3 Diag2 Diag3 Diag4 Q4 Diag5 Diag4 Diag6 Diag7 Q5 Diag8 Diag5
Q6 Diag6 Reset Q7 Diag7 Q8 Diag8
VDG
CH3 CH4 OUT4
CH5
CH6
OUT5 OUT6 OUT7 OUT8
GND
NRES
VCC
Reset
Undervoltage RESET
CH7
CH8
GND
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2 Pins Description and Connection Diagrams
L9826
2
2.1
Pins Description and Connection Diagrams
Pin description
Table 1.
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin description
Pin Out 6 Out 1 NRes NCS GND GND NON1 SDO Out 8 Out 3 Out 5 Out 2 SDI CLK GND GND NON2 VCC Out 7 Out 4 Description output 6 output 1 asynchronous reset chip select (active low) device ground device ground control input 1 serial data output output 8 output 3 output 5 output 2 serial data input serial clock device ground device ground control input 2 supply voltage output 7 output 4
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2 Pins Description and Connection Diagrams
2.2
Pins connection
Figure 2. Connection diagram
OUT6 OUT1 nRES NCS GND GND NON1 SDO OUT8 OUT3
1 2 3 4 5 6 7 8 9 10
PINCON_L9826
20 19 18 17 16 15 14 13 12 11
OUT4 OUT7 Vcc NON2 GND GND CLK SDI OUT2 OUT5
2.3
Thermal data
Table 2.
Symbol Thermal shutdown TJSC
Thermal shutdown threshold
Thermal data
Parameter Test Condition Min. Typ. Max. Unit
150
165
C
Thermal resistance RthjA-one RthjA-all Rthj-pin Single output (junction ambient) All outputs (junction ambient) Junction to Pin 90 75 18 C/W C/W C/W
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3 Electrical Specifications
L9826
3
3.1
Electrical Specifications
Absolute maximum ratings
Table 3.
Symbol VCC
For voltages and currents applied externally to the device
Parameter Supply voltage Test Condition Min. -0.3 Typ. Max. 7 Unit V
Inputs and data lines (NONx, NCS, CLK, SDI, nRes) VIN IIN Voltage (NONx, NCS, CLK, SDI, nRes) Protection diodes current 1) T 1ms
-0.3 -20
7 20
V mA
Outputs (Out1 ... Out8) VOUTc IOUT EOUTcl Continuous output voltage Output current 2) Output clamp energy IOUT 150mA -0.7 -2 45 1.0 10 V A mJ
Note: 1 All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV. It corresponds to a dissipated energy E 0,2mJ. 2 Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3. Figure 3.
Symbol
For currents determined within the device:
Parameter Test Condition Min. Typ. Max. Unit
Outputs (Out1 ... Out8) Output current (Out1, Out2) IOUT Output current (Out3 ... Out8) Tamb = 60C 2.0 ILIM ISCB A A A
IOUT1 Total average-current all i = 1-8 outputs 3)
3 When operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may occur.
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3 Electrical Specifications
3.2
Table 4.
Symbol
Electrical characteristics
Electrical Characteristcs (4.5V VCC 5,5V; -40C TJ 150C; unless otherwise specified).
Parameter Test Condition Min. Typ. Max. Unit
Supply voltage IccSTB Standby current without load (nRes = Low) IOUT1 ... 8 = 500mA IccOPM Operating mode SPI - CLK = 3MHz NCS = LOW SDO no load Iout = -2A Reset of all registers and disable of all outputs 3 5 mA 70 A
ICC
ICC during reverse output current
100 4
mA V
VDDRES Undervoltage Reset Inputs (NONx. NCS, CLK, SDI, nRes) VINL VINH Vhyst Low level High level Hysteresis voltage
-0.3 0.7*VCC 0.85 NONx, NCS, CLK, SDI VIN = VCC NRES (VIN = 0V) -10 50
0.2*VCC VCC +0,3
V V V
10
A A
IIN
Input current
RIN CIN
Pullup resistance
(NONx, NCS, CLK, SDI) Pulldown resistance (NRes) Guaranteed by design
250 10
k pF
Input capacitance
Serial data outputs VSDOH VSDOL ISDOL CSDO High output level Low output level Tristate leakage current Output capacitance ISDO = -4mA ISDO = 3,2mA NCS = high; 0V VSDO VCC fSDO = 300kHz, Guaranteed by design -10 VCC -0.4 0.4 10 10 V V A pF
Outputs OUT 1 ... 8 IOUTL1 - 8 Leakage current IOUTL1 - 8 Leakage current OUTx = OFF; VOUTx = 25V; VCC = 5V OUTx = OFF; VOUTx = 16V; VCC = 5V 100 A A
100
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3 Electrical Specifications
L9826
Table 4.
Symbol
Electrical Characteristcs (continued) (4.5V VCC 5,5V; -40C TJ 150C; unless otherwise specified).
Parameter Test Condition OUTx = OFF; VOUTx = 16V; VCC = 1V 1mA Iclp Ioutp; Itest = 10mA with correlation IOUT = 250mA; Tj = +150C VOUT = 16V; f = 1MHz guaranteed by design 45 Min. Typ. Max. 10 62 3.0 300 Unit A V pF
IOUTL1 - 8 Leakage current Vclp RDSon COUT Output clamp voltage On resistance OUT 1 ... 8 Output capacitance
Outputs short circuit protection ISBC ILIM tSCB Overcurrent shutoff threshold Short circuit current limitation Delay shutdown OUT3 ... OUT8 OUT1; OUT2 0.45 0.5 0.2 3,0 1.1 1.1 12 A A s
Diagnostics VDG IOL tdf Diagnostic threshold voltage Open load detection sink current Diagnostic detection filter time Vout = VDG for output 1 & 2 on each diagnostic condition 0.32 *VCC 20 15 0.4*VCC 100 50 V A s
Outputs timing NON1, 2 = 50% to VOUT = 0,9*Vbat tdon1 Turn ON delay of OUT 1 and 2 NCS = 50% to VOUT = 0,9*Vbat (VBAT = 16V, RL = 500) tdon2 Turn ON delay of OUT 3 to 8 NCS = 50% to VOUT = 0,9*Vbat (VBAT = 16V, RL = 500) NCS = 50% to VOUT = 0,1*Vbat tdoff Turn OFF delay of OUT 1 to 8 NON1, 2 = 50% to VOUT = 0,1*Vbat (VBAT = 16V, RL = 500) dUon1/dt Turn ON voltage slew-rate dUon2/dt Turn ON voltage slew-rate dUoff1/dt Turn OFF voltage slew-rate dUoff2/dt Turn OFF voltage slew-rate For output 3 to 8; 90% to 30% of Vbat; RL = 500; Vbat = 16V For output 1 and 2; 90% to 30% of Vbat; RL = 500; Vbat = 16V For output 1 to 8; 30% to 90% of Vbat; RL = 500; Vbat = 16V For output 1 to 8; 30% to 80% of Vbat; RL = 500; Vbat = 0.9 * Vclp 0.7 2 2 2 3.5 10 10 15 V/s V/s V/s V/s 10 s 10 s 5 s
Serial diagnostic link (Load capacitor at SDO = 100pF)
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Table 4.
Symbol fclk tclh tcll tpcld tcsdv tsclch thclcl tscld thcld tsclcl thclch tpchdz
3 Electrical Specifications
Electrical Characteristcs (continued) (4.5V VCC 5,5V; -40C TJ 150C; unless otherwise specified).
Parameter Clock frequency Minimum time CLK = HIGH Minimum time CLK = LOW Propagation delay CLK to data at SDO valid NCS = LOW to data at SDO active CLK low before NCS low CLK change L/H after NCS = low SDI input setup time SDI input hold time CLK low before NCS high CLK high after NCS high NCS L/H to output data float NCS pulse filter time Multiple of 8 CLK cycles inside NCS period CLK change H/L after SDI data valid SDI data hold after CLK change H/L 150 150 100 Setup time CLK to NCS change H/L 100 100 20 20 4,9V VCC 5,1V Test Condition 50% duty cycle 160 160 100 100 Min. Typ. Max. 3 Unit MHz ns ns ns ns ns ns ns ns ns ns ns
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4 Functional Description
L9826
4
4.1
Functional Description
General
The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the device using the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled parallel or serial. The power outputs features voltage clamping function for flyback current recirculation and are protected against short circuit to Vbat. The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and thermal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to GND in switch-off condition for all outputs. The outputs status can be read out via the serial interface. The chip internal reset is a OR function of the external nRes signal and internally generated undervoltage nRes signal.
4.2
Output Stages Control
Each output is controlled with its latch and with common reset line, which enables all eight outputs. Outputs 1 and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM control independently on the SPI. These inputs features internal pull-up resistors to assure that the outputs are switched off, when the inputs are open. The control data are transmitted via the SDI input, the timing of the serial interface is shown in Figure 4.. The device is selected with low NCS signal and the input data are transferred into the 8 bit shift register at every falling CLK edge. The rising edge of the NCS latches the new data from the shift register to the drivers.
Figure 4.
Timing of the Serial Interface
NCS
tsclch thclcl tclh tcll tsclcl thclch
CLK
tcsdv tpcld not defined tscld D8 thcld tpchdz D1
SDO
SDI
D8
D7
D1
The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since the last NCS falling edge. The NCS changes only at low CLK.
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Outputs Control Tables : Table 5.
Outputs 1, 2: NON1, 2 SPI-bit 1, 2 Output 1, 2 1 0 off 0 0 on 0 1 on 1 1 on
4 Functional Description
Outputs 3 to 8:
SPI-bit 3 ... 8 Output 3 ... 8
0 off
1 on
Figure 5.
Output control register structure
MSB Q2 Q4 Q6 Q8 Q1 Q3 Q5 LSB Q7
Control-bit output 7 Control-bit output 5 Control-bit output 3 Control-bit output 1 Control-bit output 8 Control-bit output 6 Control-bit output 4 Control-bit output 2
4.3
Power outputs characteristics
for flyback current, outputs short circuit protection and diagnostics For output currents flowing into the circuit the output voltages are limited. The typical value of this voltage is 50V. This function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is absorbed in the chip. Output short circuit protection for outputs 3 to 8 (dedicated for loads without inrush current): when the output current exceeds the short circuit threshold, the corresponding output overload latch is set and the output is switched off immediately. Output short circuit protection for outputs 1 and 2 (dedicated for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode. The output current is determined by the output characteristics and the output voltage depends on the load resistance. In this mode high power is dissipated in the output transistor and its temperature increases rapidly. When the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and the corresponding output switched off. For the load diagnostic in output off condition each output features a diagnostic current sink, typ 60A.
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4 Functional Description
L9826
4.4
Diagnostics
The output voltage at all outputs is compared with the diagnostic threshold, typ 0,38 * VCC. Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and latched. The fault latches are cleared during NCS low. The latch stores the status bit, so the first reading after the error occurred might be wrong. The second reading is right. Table 6. Diagnostic Table for outputs 1 and 2 in parallel controlled mode:
Output-voltage > DG-threshold < DG-threshold < DG-threshold > DG-threshold Status-bit high low high low Output-mode correct operation fault condition 2) correct operation fault condition 1)
Output 1, 2 off off on on
Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output exceeds the diagnostics threshold. The output operates in current regulation mode or has been switched off due to thermal shutdown. The status bit is low. Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic current source, the load is interrupted. The diagnostic bit is low. For outputs 3 to 8 the output status signals, are fed directly to the SPI register.
Table 7.
Diagnostic Table for outputs 1 to 8 in SPI controlled mode:
Output-voltage > DG-threshold < DG-threshold < DG-threshold > DG-threshold Status-bit high low low high Output-mode correct operation fault condition 2) correct operation fault condition 1)
Output 1 ... 8 off off on on
The fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. The diagnostic bit is high. Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and 2. At the falling edge of NCS the output status data are transferred to the shift register. When NSC is low, data bits contained in the shift register are transferred to SDO output et every rising CLK edge.
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Figure 6. The Pulse Diagram to Read the Outputs Status Register
4 Functional Description
NCS CLK SDO SDI MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
MSB
Table 8.
The Structure of the Outputs Status Register
MSB
LSB
Diag2 Diag4 Diag6 Diag8 Diag1 Diag3 Diag5 Diag7
Diagnostic-bit output 7 Diagnostic-bit output 5 Diagnostic-bit output 3 Diagnostic-bit output 1 Diagnostic-bit output 8 Diagnostic-bit output 6 Diagnostic-bit output 4 Diagnostic-bit output 2
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5 Application Information
L9826
5
Application Information
The typical application diagram is shown in Figure 7..
Figure 7.
Typical Application Circuit Diagram for the L9826 Circuit
VCC VOLTAGE REGULATOR VBAT
VCC
VCC
OUT1
1
2
NON1
Q1
3
S
Latch / Driver
R Overtemperature Detection
+ -
IOL
Diag1
Fault Latch
VDG
CH1 NON2
VCC
Q2 Diag2
CH2
OUT2 OUT3
SPI Interface
Output Latch
NCS
VCC
CLK
VCC
Shift Register
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q3
S
Latch / Driver
IOL
R
+ -
SDI
SDO
VCC
Diag1 Diag3 Diag2 Diag3 Diag4 Q4 Diag5 Diag4 Diag6 Diag7 Q5 Diag8 Diag5
VDG
CH3 CH4 OUT4
CH5 CH6 CH7
OUT5 OUT6 OUT7 OUT8
GND
Q6 Diag6
Reset Q7 Diag7 Q8 Diag8
P
NCS2 ... 7 CLOCK NRES SDO SDI
nRES
VCC
Reset
Undervoltage RESET
CH8
L9826
GND
R, L loads
L9826
For higher current driving capability two outputs of the same kind can be paralleled. In this case the maximum flyback energy should not exceed the limit value for single output. The immunity of the circuit with respect to the transients at the output is verified during the characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses are coupled to the outputs with 200pF series capacitor. All outputs withstand testpulses without damage. The correct function of the circuit with the Test Pulses coupled to the outputs is verified during the characterization for the typical application with R = 30 to 100, L= 0 to 600mH loads. The Test Pulses are coupled to the outputs with 200pF series capacitor.
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6 Package Informations
6
Figure 8.
Package Informations
PowerSO20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
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7 Revision history
L9826
7
Revision history
Date 22 April 2004 26 July 2005 Revision 7 8 Initial release in EDOCS. Updated the Layout look & feel. Modify value RON in Features Changes
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7 Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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